From: Thiemo Seufer Date: Thu, 22 Apr 2004 17:58:57 +0000 (+0000) Subject: * config/tc-mips.c (hilo_interlocks, gpr_interlocks, X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24772049ed946f99d2ae9cf157129c63ecadb322;p=binutils-gdb.git * config/tc-mips.c (hilo_interlocks, gpr_interlocks, cop_interlocks): Remove superfluous CPU entries. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 2b7977a760c..672bc686c1b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2004-04-22 Thiemo Seufer + + * config/tc-mips.c (hilo_interlocks, gpr_interlocks, + cop_interlocks): Remove superfluous CPU entries. + 2004-04-22 Paul Brook * config/tc-arm.c (mav_parse_offset): Value must be multiple of 4. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 7b6cee85df4..80fb607789f 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -346,7 +346,6 @@ static int mips_32bitmode = 0; || mips_opts.arch == CPU_R10000 \ || mips_opts.arch == CPU_R12000 \ || mips_opts.arch == CPU_RM7000 \ - || mips_opts.arch == CPU_SB1 \ || mips_opts.arch == CPU_VR5500 \ ) @@ -357,8 +356,6 @@ static int mips_32bitmode = 0; level I. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ - || mips_opts.arch == CPU_VR5400 \ - || mips_opts.arch == CPU_VR5500 \ || mips_opts.arch == CPU_R3900) /* Whether the processor uses hardware interlocks to avoid delays @@ -374,9 +371,6 @@ static int mips_32bitmode = 0; && mips_opts.isa != ISA_MIPS2 \ && mips_opts.isa != ISA_MIPS3) \ || mips_opts.arch == CPU_R4300 \ - || mips_opts.arch == CPU_VR5400 \ - || mips_opts.arch == CPU_VR5500 \ - || mips_opts.arch == CPU_SB1 \ ) /* Whether the processor uses hardware interlocks to protect reads