From: lkcl Date: Tue, 3 Sep 2019 21:39:41 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~4163 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24802b5a1ff181b1f73c938597e292302f4868be;p=libreriscv.git --- diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn index abcd595bd..97a6fe1ee 100644 --- a/simple_v_extension/vblock_format/discussion.mdwn +++ b/simple_v_extension/vblock_format/discussion.mdwn @@ -41,7 +41,7 @@ registers. The reason why Twin-SVP's prefix is only P48 is because P64 can chang VL/MVL from a P64 prefix is applied as if a [[specification/sv.setvl]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK. This *includes* modification of SV CSR STATE. -itype is described in [[sv_prefix_ptoposal]]. The additional itype on the src operand(s) allows, for example, a LD of 8 bit vectors to be auto-converted to 16 bit signed in a single instruction. More examples on elwidth polymorphism is in the [[appendix]]. +itype is described in [[sv_prefix_proposal]]. The additional itype on the src operand(s) allows, for example, a LD of 8 bit vectors to be auto-converted to 16 bit signed in a single instruction. More examples on elwidth polymorphism is in the [[appendix]]. # Rules