From: Sebastien Bourdeauducq Date: Thu, 4 Oct 2012 18:10:24 +0000 (+0200) Subject: actorlib/spi: fix memory port we/wd X-Git-Tag: 24jan2021_ls180~2099^2~830 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24877f271bdec534e8c213d2b4738f47bc0f20a2;p=litex.git actorlib/spi: fix memory port we/wd --- diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py index 62c742dd..8f44f0b0 100644 --- a/migen/actorlib/spi.py +++ b/migen/actorlib/spi.py @@ -24,7 +24,7 @@ class Collector(Actor): dummy = Signal(BV(self._dw)) wd = Signal(BV(self._dw)) we = Signal() - wp = MemoryPort(wa, dummy, wd, we) + wp = MemoryPort(wa, dummy, we, wd) ra = Signal(BV(bits_for(self._depth-1))) rd = Signal(BV(self._dw)) rp = MemoryPort(ra, rd)