From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 18 Oct 2018 08:54:03 +0000 (+0200)
Subject: Merge pull request #657 from mithro/xilinx-vpr
X-Git-Tag: yosys-0.9~441
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24a5c6585678f89058382fe2c3f36b821b419e90;p=yosys.git

Merge pull request #657 from mithro/xilinx-vpr

xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
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24a5c6585678f89058382fe2c3f36b821b419e90