From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 18:09:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~553
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24aca572ccac86d264519a63a88e1a5524db5dff;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 429dc1aa5..4d278e3ca 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -24,6 +24,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
 * <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
 * <https://bugs.libre-soc.org/show_bug.cgi?id=636> add zeroing and exceptions
+* <https://bugs.libre-soc.org/show_bug.cgi?id=663> element-width overrides
 
 # Code to convert
 
@@ -227,7 +228,14 @@ Progress:
 
 ## Element width overrides
 
-TODO
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
 
 ## Reduce Mode