From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 6 Sep 2020 16:33:48 +0000 (+0100)
Subject: redo generation of microwatt.v from litex
X-Git-Tag: semi_working_ecp5~170
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24c673c5dfdf64dbb0ea641fa89f122ce042144b;p=soc.git

redo generation of microwatt.v from litex
---

diff --git a/src/soc/litex/florent/microwatt/microwatt.v b/src/soc/litex/florent/microwatt/microwatt.v
index 21a5e6e2..87dfc352 100644
--- a/src/soc/litex/florent/microwatt/microwatt.v
+++ b/src/soc/litex/florent/microwatt/microwatt.v
@@ -1,4 +1,4 @@
-/* Generated by Yosys 0.9+2406 (git sha1 2f50c5af, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os) */
+/* Generated by Yosys 0.9+3558 (git sha1 c66d1dfa, clang 9.0.1-12 -fPIC -Os) */
 
 module cache_ram_8_64_1489f923c4dca729178b3e3233458550d8dddf29(clk, rd_en, rd_addr, wr_sel, wr_addr, wr_data, rd_data);
   wire [2047:0] _00_;
@@ -133,7 +133,7 @@ module cache_ram_8_64_3f29546453678b855931c174a97d6c0894b8f546(clk, rd_en, rd_ad
   reg [7:0] \$mem$\20466  [255:0];
   reg [7:0] \$mem$\20467  [255:0];
   always @(posedge clk)
-      _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
+    _00_ <= { _16_, _14_, _12_, _10_, _08_, _06_, _04_, _02_ };
   (* ram_style = "block" *)
   reg [7:0] \20460  [255:0];
   reg [7:0] _17_;
@@ -295,9 +295,9 @@ module control_1(clk, rst, complete_in, valid_in, flush_in, stall_in, sgl_pipe_i
   assign _06_ = ~ 1'h1;
   assign _07_ = _06_ | _05_;
   always @(posedge clk)
-      _08_ <= _07_;
+    _08_ <= _07_;
   always @(posedge clk)
-      r_int <= { _54_, _50_ };
+    r_int <= { _54_, _50_ };
   assign _09_ = ~ flush_in;
   assign _10_ = valid_in & _09_;
   assign _11_ = ~ stall_in;
@@ -506,25 +506,25 @@ module core_71ba14ecdd9e9507b1aeafd985ac12164cac4c4e(clk, rst, alt_reset, wishbo
   assign decode2_stall_in = ex1_stall_out | ls1_stall_out;
   assign core_rst = dbg_core_rst | rst;
   always @(posedge clk)
-      rst_fetch1 <= core_rst;
+    rst_fetch1 <= core_rst;
   always @(posedge clk)
-      rst_fetch2 <= core_rst;
+    rst_fetch2 <= core_rst;
   always @(posedge clk)
-      rst_icache <= core_rst;
+    rst_icache <= core_rst;
   always @(posedge clk)
-      rst_dcache <= core_rst;
+    rst_dcache <= core_rst;
   always @(posedge clk)
-      rst_dec1 <= core_rst;
+    rst_dec1 <= core_rst;
   always @(posedge clk)
-      rst_dec2 <= core_rst;
+    rst_dec2 <= core_rst;
   always @(posedge clk)
-      rst_ex1 <= core_rst;
+    rst_ex1 <= core_rst;
   always @(posedge clk)
-      rst_ls1 <= core_rst;
+    rst_ls1 <= core_rst;
   always @(posedge clk)
-      rst_dbg <= rst;
+    rst_dbg <= rst;
   always @(posedge clk)
-      alt_reset_d <= alt_reset;
+    alt_reset_d <= alt_reset;
   assign fetch1_stall_in = icache_stall_out | decode2_stall_out;
   assign _1_ = dbg_icache_rst | ex1_icache_inval;
   cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f cr_file_0 (
@@ -831,19 +831,19 @@ module core_debug(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_
   assign _47_ = rst ? 1'h0 : _41_;
   assign _48_ = rst ? gspr_index : _33_;
   always @(posedge clk)
-      dmi_req_1 <= _42_;
+    dmi_req_1 <= _42_;
   always @(posedge clk)
-      stopping <= _43_;
+    stopping <= _43_;
   always @(posedge clk)
-      do_step <= _44_;
+    do_step <= _44_;
   always @(posedge clk)
-      do_reset <= _45_;
+    do_reset <= _45_;
   always @(posedge clk)
-      do_icreset <= _46_;
+    do_icreset <= _46_;
   always @(posedge clk)
-      terminated <= _47_;
+    terminated <= _47_;
   always @(posedge clk)
-      gspr_index <= _48_;
+    gspr_index <= _48_;
   assign _49_ = ~ do_step;
   assign _50_ = stopping & _49_;
   assign dmi_dout = _08_;
@@ -886,10 +886,10 @@ module cr_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, sim_dum
   assign xerc_updated = w_in[41] ? w_in[46:42] : xerc;
   assign _8_ = w_in[0] ? { _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ } : crs;
   always @(posedge clk)
-      crs <= _8_;
+    crs <= _8_;
   assign _9_ = w_in[41] ? xerc_updated : xerc;
   always @(posedge clk)
-      xerc <= _9_;
+    xerc <= _9_;
   assign d_out = { xerc_updated, _7_, _6_, _5_, _4_, _3_, _2_, _1_, _0_ };
 endmodule
 
@@ -909,7 +909,7 @@ module cr_hazard_1(clk, stall_in, cr_read_in, cr_write_in, stall_out);
   assign _0_ = ~ stall_in;
   assign _1_ = _0_ ? cr_write_in : r;
   always @(posedge clk)
-      r <= _1_;
+    r <= _1_;
   assign _2_ = r == cr_read_in;
   assign _3_ = _2_ ? 1'h1 : 1'h0;
   assign _4_ = ~ cr_read_in;
@@ -4844,9 +4844,9 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0011_ = rst ? r0[146:1] : _0008_[146:1];
   assign _0012_ = rst ? 1'h0 : _0009_;
   always @(posedge clk)
-      _0013_ <= _0004_;
+    _0013_ <= _0004_;
   always @(posedge clk)
-      r0 <= { _0011_, _0010_ };
+    r0 <= { _0011_, _0010_ };
   assign _0014_ = ~ _0409_;
   assign _0015_ = r0[0] & _0014_;
   assign _0016_ = ~ _0509_[0];
@@ -4855,7 +4855,7 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0018_ = _0409_ ? r0[24:19] : _0017_;
   assign _0019_ = 6'h3f - _0018_;
   always @(posedge clk)
-      tlb_valid_way <= _0652_;
+    tlb_valid_way <= _0652_;
   assign _0020_ = { 26'h0000000, r0[24:19] } == 32'd0;
   assign _0021_ = tlb_hit & _0020_;
   assign \maybe_tlb_plrus.tlb_plrus%0.tlb_plru_acc_en  = _0021_ ? 1'h1 : 1'h0;
@@ -5074,7 +5074,7 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0165_ = _0155_ ? _0160_ : _0164_;
   assign _0166_ = _0158_ ? 128'h00000000000000000000000000000000 : _0165_;
   always @(posedge clk)
-      dtlb_valids <= _0166_;
+    dtlb_valids <= _0166_;
   assign _0167_ = ~ _0158_;
   assign _0168_ = ~ _0155_;
   assign _0169_ = _0167_ & _0168_;
@@ -5397,7 +5397,7 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0420_ = _0418_ ? 1'h0 : _0419_[0];
   assign _0421_ = _0418_ ? reservation[58:1] : _0419_[58:1];
   always @(posedge clk)
-      reservation <= { _0421_, _0420_ };
+    reservation <= { _0421_, _0420_ };
   assign _0422_ = 1'h1 - _0508_[144];
   assign _0423_ = 1'h1 - _0508_[144];
   assign _0424_ = _0629_[64] & _0629_[65];
@@ -5493,9 +5493,9 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0506_ = r0[143] | r0[145];
   assign _0507_ = r0_valid & _0506_;
   always @(posedge clk)
-      _0508_ <= { _0501_, _0500_, _0498_ };
+    _0508_ <= { _0501_, _0500_, _0498_ };
   always @(posedge clk)
-      _0509_ <= { _0507_, _0505_ };
+    _0509_ <= { _0507_, _0505_ };
   assign _0510_ = req_op == 3'h1;
   assign _0511_ = 5'h1f - r0[17:13];
   assign _0512_ = 32'd0 == { 31'h00000000, replace_way };
@@ -6198,11 +6198,11 @@ module dcache_64_32_2_64_2_12(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, s
   assign _0627_ = rst ? 2'h0 : { _0614_, _0613_ };
   assign _0628_ = rst ? _0629_[189:167] : { _0619_, _0618_, _0617_, _0616_, _0615_ };
   always @(posedge clk)
-      cache_tags <= _0620_;
+    cache_tags <= _0620_;
   always @(posedge clk)
-      cache_valids <= _0621_;
+    cache_valids <= _0621_;
   always @(posedge clk)
-      _0629_ <= { _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_ };
+    _0629_ <= { _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_ };
   (* ram_style = "distributed" *)
   reg [91:0] \13892  [63:0];
   reg [91:0] _3675_;
@@ -8805,7 +8805,7 @@ module decode1(clk, rst, stall_in, flush_in, f_in, d_out);
   assign _02_ = _00_ | _01_;
   assign _03_ = _02_ ? rin : r;
   always @(posedge clk)
-      r <= _03_;
+    r <= _03_;
   assign _04_ = r[117:112] == 6'h3d;
   assign _05_ = _04_ ? 1'h0 : 1'h1;
   assign _06_ = f_in[98:93] == 6'h1f;
@@ -11288,7 +11288,7 @@ module decode2_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, complete_in, s
   output stall_out;
   output stopped_out;
   always @(posedge clk)
-      r <= rin;
+    r <= rin;
   assign _02_ = d_in[103] ? d_in[103:98] : { 1'h0, d_in[86:82] };
   assign _03_ = d_in[109] ? d_in[109:104] : { 1'h0, d_in[81:77] };
   assign _04_ = d_in[120:118] == 3'h1;
@@ -11680,27 +11680,27 @@ module divider(clk, rst, d_in, d_out);
   assign _49_ = rst ? overflow : _38_;
   assign _50_ = rst ? ovf32 : _39_;
   always @(posedge clk)
-      dend <= _40_;
+    dend <= _40_;
   always @(posedge clk)
-      div <= _41_;
+    div <= _41_;
   always @(posedge clk)
-      quot <= _42_;
+    quot <= _42_;
   always @(posedge clk)
-      running <= _43_;
+    running <= _43_;
   always @(posedge clk)
-      count <= _44_;
+    count <= _44_;
   always @(posedge clk)
-      neg_result <= _45_;
+    neg_result <= _45_;
   always @(posedge clk)
-      is_modulus <= _46_;
+    is_modulus <= _46_;
   always @(posedge clk)
-      is_32bit <= _47_;
+    is_32bit <= _47_;
   always @(posedge clk)
-      is_signed <= _48_;
+    is_signed <= _48_;
   always @(posedge clk)
-      overflow <= _49_;
+    overflow <= _49_;
   always @(posedge clk)
-      ovf32 <= _50_;
+    ovf32 <= _50_;
   assign result = is_modulus ? dend[128:65] : quot;
   assign _51_ = - $signed({ 1'h0, result });
   assign sresult = neg_result ? _51_ : { 1'h0, result };
@@ -11720,7 +11720,7 @@ module divider(clk, rst, d_in, d_out);
   assign _63_ = count == 7'h40;
   assign _64_ = _63_ ? 1'h1 : 1'h0;
   always @(posedge clk)
-      _65_ <= { did_ovf, oresult, _64_ };
+    _65_ <= { did_ovf, oresult, _64_ };
   assign d_out = _65_;
 endmodule
 
@@ -12866,11 +12866,11 @@ module execute1_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, e_in, l_in, e
   assign _0010_ = rst ? ctrl[320:193] : _0762_[128:1];
   assign _0011_ = rst ? 1'h0 : 1'h1;
   always @(posedge clk)
-      _0012_ <= _0006_;
+    _0012_ <= _0006_;
   always @(posedge clk)
-      r <= _0007_;
+    r <= _0007_;
   always @(posedge clk)
-      ctrl <= { _0010_, _0009_, _0008_ };
+    ctrl <= { _0010_, _0009_, _0008_ };
   assign _0013_ = r[114] ? r[119:115] : e_in[322:318];
   assign _0014_ = e_in[334] ? { b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31], b_in[31:0], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31], a_in[31:0] } : { 33'h000000000, b_in[31:0], 33'h000000000, a_in[31:0] };
   assign _0015_ = e_in[334] ? { b_in[63], b_in, a_in[63], a_in } : { 1'h0, b_in, 1'h0, a_in };
@@ -16939,9 +16939,9 @@ module fetch1_3f28fda38b1ec2f6fdb16c0bce5a53c28d1424e5(clk, rst, stall_in, flush
   input stall_in;
   input stop_in;
   always @(posedge clk)
-      r <= { _21_, stop_in, _20_, _22_ };
+    r <= { _21_, stop_in, _20_, _22_ };
   always @(posedge clk)
-      r_int <= r_next_int;
+    r_int <= r_next_int;
   assign _00_ = alt_reset_in ? 64'h0000000000000000 : 64'h0000000000000000;
   assign _01_ = ~ stall_in;
   assign _02_ = stop_in ? 2'h1 : r_int;
@@ -17032,10 +17032,10 @@ module fetch2(clk, rst, stall_in, flush_in, i_in, f_out);
   assign _01_ = ~ stall_in;
   assign _02_ = _00_ | _01_;
   always @(posedge clk)
-      r_int <= { r_int[100], _17_, _06_[98:3], _12_, _06_[1], _11_ };
+    r_int <= { r_int[100], _17_, _06_[98:3], _12_, _06_[1], _11_ };
   assign _03_ = _02_ ? { _10_[98:3], _15_, _10_[1], _16_ } : r;
   always @(posedge clk)
-      r <= _03_;
+    r <= _03_;
   assign _04_ = ~ r_int[99];
   assign _05_ = stall_in & _04_;
   assign _06_ = _05_ ? { 1'h1, i_in } : r_int[99:0];
@@ -17077,7 +17077,7 @@ module gpr_hazard_1(clk, stall_in, gpr_write_valid_in, gpr_write_in, bypass_avai
   output stall_out;
   output use_bypass;
   always @(posedge clk)
-      r <= rin;
+    r <= rin;
   assign _00_ = r[7:2] == gpr_read_in;
   assign _01_ = r[0] & _00_;
   assign _02_ = ~ stall_in;
@@ -19089,11 +19089,11 @@ module icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst
   assign _0604_ = _0603_ ? 1'h1 : _0606_[123];
   assign _0605_ = _0601_ ? 1'h0 : _0604_;
   always @(posedge clk)
-      cache_tags <= _0593_;
+    cache_tags <= _0593_;
   always @(posedge clk)
-      cache_valids <= _0594_;
+    cache_valids <= _0594_;
   always @(posedge clk)
-      _0606_ <= { _0605_, _0599_, _0598_, _0597_, _0596_, _0595_ };
+    _0606_ <= { _0605_, _0599_, _0598_, _0597_, _0596_, _0595_ };
   (* ram_style = "distributed" *)
   reg [63:0] \1287  [63:0];
   always @(posedge clk) begin
@@ -20209,7 +20209,7 @@ module icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst
   assign _0506_ = m_in[1] ? { _0825_, _0824_, _0823_, _0822_, _0821_, _0820_, _0819_, _0818_, _0817_, _0816_, _0815_, _0814_, _0813_, _0812_, _0811_, _0810_, _0809_, _0808_, _0807_, _0806_, _0805_, _0804_, _0803_, _0802_, _0801_, _0800_, _0799_, _0798_, _0797_, _0796_, _0795_, _0794_, _0793_, _0792_, _0791_, _0790_, _0789_, _0788_, _0787_, _0786_, _0785_, _0784_, _0783_, _0782_, _0781_, _0780_, _0779_, _0778_, _0777_, _0776_, _0775_, _0774_, _0773_, _0772_, _0771_, _0770_, _0769_, _0768_, _0767_, _0766_, _0765_, _0764_, _0763_, _0762_ } : _0505_;
   assign _0507_ = _0502_ ? 64'h0000000000000000 : _0506_;
   always @(posedge clk)
-      itlb_valids <= _0507_;
+    itlb_valids <= _0507_;
   assign _0508_ = ~ _0502_;
   assign _0509_ = ~ m_in[1];
   assign _0510_ = _0508_ & _0509_;
@@ -20247,7 +20247,7 @@ module icache_64_32_2_64_12_56_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, rst
   assign _0539_ = req_is_hit ? req_hit_way : _0541_[0];
   assign _0540_ = req_is_hit ? i_in[3] : i_in[3];
   always @(posedge clk)
-      _0541_ <= { req_is_hit, _0540_, i_in[67:4], _0539_ };
+    _0541_ <= { req_is_hit, _0540_, i_in[67:4], _0539_ };
   plru_1 \maybe_plrus.plrus%0.plru  (
     .acc(req_hit_way),
     .acc_en(\maybe_plrus.plrus%0.plru_acc_en ),
@@ -21124,7 +21124,7 @@ module loadstore1(clk, rst, l_in, d_in, m_in, dc_stall, e_out, l_out, d_out, m_o
   assign _002_ = rst ? 3'h0 : _292_;
   assign _003_ = rst ? r[338:225] : { _294_[112], _320_, _294_[15:0], _293_ };
   always @(posedge clk)
-      r <= { _003_, _002_, _001_ };
+    r <= { _003_, _002_, _001_ };
   assign _004_ = | r[241:234];
   assign _005_ = r[202:200] - 3'h1;
   assign _006_ = r[204] ? _005_ : 3'h0;
@@ -24184,7 +24184,7 @@ module mmu(clk, rst, l_in, d_in, l_out, d_out, i_out);
   assign _009_ = rst ? 1'h0 : _272_;
   assign _010_ = rst ? r[433:298] : { _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_ };
   always @(posedge clk)
-      r <= { _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
+    r <= { _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_, _001_ };
   assign _011_ = r[303:302] == 2'h0;
   assign _012_ = r[303:302] == 2'h1;
   function [30:0] \9811 ;
@@ -24304,9 +24304,9 @@ module multiply_16(clk, m_in, m_out);
   output [65:0] m_out;
   reg [2207:0] r = 2208'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
   always @(posedge clk)
-      m <= m_in;
+    m <= m_in;
   always @(posedge clk)
-      r <= { m[137], _00_, m[6:0], r[2207:138] };
+    r <= { m[137], _00_, m[6:0], r[2207:138] };
   assign _00_ = $signed({ m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71], m[71:7] }) * $signed({ m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136], m[136:72] });
   assign _01_ = | r[208:176];
   assign _02_ = & r[208:176];
@@ -24380,7 +24380,7 @@ module plru_1(clk, rst, acc, acc_en, lru);
   assign _3_ = acc_en ? { _8_, _7_ } : tree;
   assign _4_ = rst ? 2'h0 : _3_;
   always @(posedge clk)
-      tree <= _4_;
+    tree <= _4_;
   assign _5_ = _0_ ? tree[1] : tree[0];
   assign _6_ = ~ _1_;
   assign _7_ = _6_ ? _2_ : tree[0];
@@ -24435,7 +24435,7 @@ module register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, d
   assign _01_ = _00_ | 1'h1;
   assign _02_ = w_in[70] ? 1'h1 : 1'h0;
   always @(posedge clk)
-      _03_ <= _01_;
+    _03_ <= _01_;
   assign _04_ = ~ d_in[7];
   assign _05_ = _04_ & dbg_gpr_req;
   assign _06_ = ~ dbg_ack;
@@ -24456,9 +24456,9 @@ module register_file_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, d_in, w_in, d
   assign _21_ = dbg_gpr_req ? _19_ : 1'h0;
   assign _22_ = _20_ ? rd_port_b : dbg_data;
   always @(posedge clk)
-      dbg_data <= _22_;
+    dbg_data <= _22_;
   always @(posedge clk)
-      dbg_ack <= _21_;
+    dbg_ack <= _21_;
   reg [63:0] \4359  [63:0];
   initial begin
     \4359 [0] = 64'h0000000000000000;
@@ -25383,7 +25383,7 @@ module zero_counter(clk, rs, count_right, is_32bit, result);
   output [63:0] result;
   input [63:0] rs;
   always @(posedge clk)
-      r <= { count_right, is_32bit, _16_, _20_ };
+    r <= { count_right, is_32bit, _16_, _20_ };
   assign _00_ = | rs[15:0];
   assign _01_ = | rs[31:16];
   assign _02_ = | rs[47:32];