From: colepoirier <colepoirier@gmail.com>
Date: Sat, 16 May 2020 21:08:48 +0000 (-0700)
Subject: Implemented luke's TODOs by adding 'reset_less' to all Signal()'s,
X-Git-Tag: div_pipeline~1124
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24d546c3fcf4f7a83c27c8b5b8883caf4d17b765;p=soc.git

Implemented luke's TODOs by adding 'reset_less' to all Signal()'s,
assigning index to a Signal() instead of a python AST fragment, fixed
formatting
---

diff --git a/src/soc/logical/bperm.py b/src/soc/logical/bperm.py
index 414678af..b7b9322e 100644
--- a/src/soc/logical/bperm.py
+++ b/src/soc/logical/bperm.py
@@ -27,23 +27,24 @@ class Bpermd(Elaboratable):
     """
 
     def __init__(self, width):
-        self.perm = Signal(width) # needs to be reset_less=True (all of them)
-        self.rs   = Signal(width)
-        self.ra   = Signal(width)
-        self.rb   = Signal(width)
+        self.perm = Signal(width, reset_less=True)
+        self.rs   = Signal(width, reset_less=True)
+        self.ra   = Signal(width, reset_less=True)
+        self.rb   = Signal(width, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        index = Signal(8)
-        signals = [ Signal(1) for i in range(64) ] # no spaces on braces [code]
-        for i,n in enumerate(signals): # add space after comma
+        index = Signal(8, reset_less=True)
+        signals = [Signal(1, reset_less=True) for i in range(64)]
+        for i, n in enumerate(signals):
             m.d.comb += n.eq(self.rb[i])
         rb64 = Array(signals) # makes this indexable dynamically (a pmux)
-        for i in range(0, 8): # remove 0,
-            index = self.rs[8 * i:8 * i + 8] # remove spaces here
-            # TODO: assign index to a Signal, use the *signal* below
-            with m.If(index < 64):
-                m.d.comb += self.perm[i].eq(rb64[index])
+        for i in range(8):
+            index = self.rs[8*i:8*i+8]
+            idx = Signal(8, name="idx%d" % i, reset_less=True)
+            m.d.comb += idx.eq(index)
+            with m.If(idx < 64):
+                m.d.comb += self.perm[i].eq(rb64[idx])
         m.d.comb += self.ra[0:8].eq(self.perm)
         return m