From: lkcl <lkcl@web>
Date: Fri, 6 Aug 2021 12:27:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~477
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24e74155227e3107d6a0db179df65ce9f514b33c;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 660fb82da..f0f16fbfd 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -186,7 +186,7 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 
 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 
-These are the modes:
+These are the modes for everything except [[sv/ldst]] and [[sv/branches]]:
 
 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.