From: Kajol Jain <kajoljain797@gmail.com>
Date: Wed, 12 Jun 2019 07:02:59 +0000 (+0530)
Subject: arch-power: Added function to modify MSR and SRR1 register
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24f367757a1d5562c84b5da006f27377c1cbd3aa;p=gem5.git

arch-power: Added function to modify MSR and SRR1 register

* Added general function to modify MSR and SRR1 register.
* Added macros to get mask for
  * Set particular bit.
  * Unset Bit.

Change-Id: I17b82f6ef7f7d8915f9c1320f99fc6f3f9ecaf74
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
---

diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index 9667639f2..bc42fbebe 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -33,6 +33,11 @@
 #include "cpu/thread_context.hh"
 #include "sim/faults.hh"
 
+#define setbit(shift, mask) ( (uint64_t)1 << shift | mask)
+#define unsetbit(shift,mask) ( ~((uint64_t)1 << shift) & mask)
+#define setBitMask(shift) ( (uint64_t)1 << shift)
+#define unsetMask(start ,end)(~((setBitMask(start))-1) | ((setBitMask(end))-1))
+
 namespace PowerISA
 {
 
@@ -91,6 +96,35 @@ class PowerInterrupt : public PowerFaultBase
         : PowerFaultBase("Interrupt")
     {
     }
+    virtual void updateMsr(ThreadContext * tc)
+      {
+        Msr msr = tc->readIntReg(INTREG_MSR);
+        msr.tm = 0;
+        msr.vec = 0;
+        msr.vsx = 0;
+        msr.fp = 0;
+        msr.pr = 0;
+        msr.pmm = 0;
+        msr.ir = 0;
+        msr.dr = 0;
+        msr.fe1 = 0;
+        msr.fe0 = 0;
+        msr.ee = 0;
+        msr.ri = 0;
+        msr.te = 0;
+        msr.sf = 1;
+        msr = unsetbit(5, msr);
+        tc->setIntReg(INTREG_MSR, msr);
+      }
+
+    virtual void updateSRR1(ThreadContext *tc, uint64_t BitMask=0x0000000)
+    {
+      Msr msr = tc->readIntReg(INTREG_MSR);
+      uint64_t srr1 = ((msr & unsetMask(31, 27)) & unsetMask(22,16)) | BitMask;
+      tc->setIntReg(INTREG_SRR1, srr1);
+    }
+};
+
 };