From: Tobias Platen <tplaten@posteo.de>
Date: Tue, 10 Sep 2019 19:35:27 +0000 (+0200)
Subject: tlb_content update test
X-Git-Tag: div_pipeline~1825
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24f824be042a6720c5c9ee621e1e3f09efda322e;p=soc.git

tlb_content update test
---

diff --git a/src/TLB/ariane/ptw.py b/src/TLB/ariane/ptw.py
index ce8c774f..4046c711 100644
--- a/src/TLB/ariane/ptw.py
+++ b/src/TLB/ariane/ptw.py
@@ -133,7 +133,7 @@ class TLBUpdate:
         self.is_2M = Signal()
         self.is_1G = Signal()
         self.is_512G = Signal()
-        self.vpn = Signal(27)
+        self.vpn = Signal(36)
         self.asid = Signal(asid_width)
         self.content = PTE()
 
diff --git a/src/TLB/ariane/test/test_tlb_content.py b/src/TLB/ariane/test/test_tlb_content.py
index 2261329f..0da2aff5 100644
--- a/src/TLB/ariane/test/test_tlb_content.py
+++ b/src/TLB/ariane/test/test_tlb_content.py
@@ -6,14 +6,17 @@ from nmigen.compat.sim import run_simulation
 
 from TLB.ariane.tlb_content import TLBContent
 
-#def set_vaddr(addr):
-#    yield dut.lu_vaddr_i.eq(addr)
-#    yield dut.update_i.vpn.eq(addr>>12)
-
+def update():
+    yield dut.replace_en_i.eq(1)
+    
 def tbench(dut):
+    yield dut.replace_en_i.eq(1)
+    yield dut.update_i.valid.eq(1)
+    yield dut.update_i.is_512G.eq(1)
+    yield dut.update_i.vpn.eq(0xFFFFFFFF)
     yield
     yield
-    yield
+    
 
 if __name__ == "__main__":
     dut = TLBContent(4,4)
diff --git a/src/TLB/ariane/tlb_content.py b/src/TLB/ariane/tlb_content.py
index 4ffd919e..4010e377 100644
--- a/src/TLB/ariane/tlb_content.py
+++ b/src/TLB/ariane/tlb_content.py
@@ -5,17 +5,17 @@ from TLB.ariane.ptw import TLBUpdate, PTE
 
 class TLBEntry:
     def __init__(self, asid_width):
-        self.asid = Signal(asid_width)
+        self.asid = Signal(asid_width,name="ent_asid")
         # SV48 defines four levels of page tables
-        self.vpn0 = Signal(9)
-        self.vpn1 = Signal(9)
-        self.vpn2 = Signal(9)
-        self.vpn3 = Signal(9)
-        self.is_2M = Signal()
-        self.is_1G = Signal()
-        self.is_512G = Signal()
-        self.valid = Signal()
-
+        self.vpn0 = Signal(9,name="ent_vpn0")
+        self.vpn1 = Signal(9,name="ent_vpn1")
+        self.vpn2 = Signal(9,name="ent_vpn2")
+        self.vpn3 = Signal(9,name="ent_vpn3")
+        self.is_2M = Signal(name="ent_is_2M")
+        self.is_1G = Signal(name="ent_is_1G")
+        self.is_512G = Signal(name="ent_is_512G")
+        self.valid = Signal(name="ent_valid")
+        
     def flatten(self):
         return Cat(*self.ports())
 
@@ -25,6 +25,7 @@ class TLBEntry:
     def ports(self):
         return [self.asid, self.vpn0, self.vpn1, self.vpn2,
                 self.is_2M, self.is_1G, self.valid]
+        
 
 class TLBContent(Elaboratable):
     def __init__(self, pte_width, asid_width):
@@ -33,6 +34,7 @@ class TLBContent(Elaboratable):
         self.flush_i = Signal()  # Flush signal
         # Update TLB
         self.update_i = TLBUpdate(asid_width)
+        self.vpn3 = Signal(9)
         self.vpn2 = Signal(9)
         self.vpn1 = Signal(9)
         self.vpn0 = Signal(9)
@@ -50,6 +52,11 @@ class TLBContent(Elaboratable):
         m = Module()
 
         tags = TLBEntry(self.asid_width)
+        #TODO signal names, RecordObject
+        print("TAGS:")
+        #print(tags)
+        
+        
         content = Signal(self.pte_width)
 
         m.d.comb += [self.lu_hit_o.eq(0),
@@ -113,6 +120,7 @@ class TLBContent(Elaboratable):
         with m.Elif(replace_valid):
             m.d.sync += [ # update tag array
                           tags.asid.eq(self.update_i.asid),
+                          tags.vpn3.eq(self.update_i.vpn[27:36]),
                           tags.vpn2.eq(self.update_i.vpn[18:27]),
                           tags.vpn1.eq(self.update_i.vpn[9:18]),
                           tags.vpn0.eq(self.update_i.vpn[0:9]),