From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Tue, 31 Aug 2010 01:54:44 +0000 (+0800)
Subject: i965: fix depth test on sandybridge
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24ff42e7d56ac489caeca6b5ffcc3091cc8194b5;p=mesa.git

i965: fix depth test on sandybridge

This includes several corrections for fixing depth test on sandybridge.
Fix wrong bits definition in depth stencil state. Fix wrong order of
state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use
buffer width parameter in depth buffer setting.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 565a9e3ee18..6eeaba77720 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -295,7 +295,7 @@ static void emit_depthbuffer(struct brw_context *brw)
 		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		0);
       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
-		((region->pitch - 1) << 6) |
+		((region->width - 1) << 6) |
 		((region->height - 1) << 19));
       OUT_BATCH(0);
 
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index cdd2998627f..2a118e01c53 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -750,7 +750,7 @@ struct gen6_depth_stencil_state
    } ds1;
 
    struct {
-      GLuint pad0:25;
+      GLuint pad0:26;
       GLuint depth_write_enable:1;
       GLuint depth_test_func:3;
       GLuint pad1:1;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index f7acad69129..26f1070a164 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -267,9 +267,9 @@ static void upload_cc_state_pointers(struct brw_context *brw)
 
    BEGIN_BATCH(4);
    OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2));
-   OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);