From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 May 2021 15:24:57 +0000 (+0100)
Subject: save SVSRR0 in trap, if SVP64 mode enabled
X-Git-Tag: 0.0.3~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25071d491dba94495657796eb6ff10eb6499257f;p=openpower-isa.git

save SVSRR0 in trap, if SVP64 mode enabled
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 42042c9d..3526643e 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -563,8 +563,11 @@ class ISACaller:
         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
         # store CIA(+4?) in SRR0, set NIA to 0x700
         # store MSR in SRR1, set MSR to um errr something, have to check spec
+        # store SVSTATE (if enabled) in SVSRR0
         self.spr['SRR0'].value = self.pc.CIA.value
         self.spr['SRR1'].value = self.namespace['MSR'].value
+        if self.is_svp64_mode:
+            self.spr['SVSRR0'] = self.namespace['SVSTATE'].value
         self.trap_nia = SelectableInt(trap_addr, 64)
         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1