From: lkcl <lkcl@web>
Date: Thu, 13 May 2021 16:08:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~922
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25131d8a1ae8d3358a9dbe78bd45cc95c8121fbe;p=libreriscv.git

---

diff --git a/conferences/ics2021.mdwn b/conferences/ics2021.mdwn
index fc6c38dc4..3de268e6c 100644
--- a/conferences/ics2021.mdwn
+++ b/conferences/ics2021.mdwn
@@ -58,8 +58,8 @@ Software Engineers have it drummed into them from either training or
 bitter experience that unit tests are critical at every level.  Whilst
 the Validation Process for an ASIC goes through a rigorous process
 in the Synthesis Tools to ensure its correctness at every step, the
-actual HDL itself, shockingly, is typically put together first and
-only on completion are high-level (binary) unit tests run.  Errors
+actual HDL itself, shockingly, is typically put together in its entirety. 
+Only on completion are high-level (binary) unit tests run.  Errors
 in a low-level subsystem thus become extremely hard to find.
 
 In addition to that, as a Libre Project, we have had to use Libre