From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 May 2018 16:13:38 +0000 (+0200)
Subject: Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
X-Git-Tag: yosys-0.8~87
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=251562a4918576bd485bcdcc908c0ac780689a77;p=yosys.git

Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 7ebcbca04..19273c69a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1393,7 +1393,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
 			return;
 	}
 
-	if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE)
+	while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE)
 	{
 		net = inst->GetInput();
 		inst = net->Driver();;