From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 May 2019 13:20:41 +0000 (+0100)
Subject: add fn-unit src/dest latch registers
X-Git-Tag: div_pipeline~2059
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2515c3f93f5524d7a4842f3dedae931bb0d9bad8;p=soc.git

add fn-unit src/dest latch registers
---

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 018c8a17..09d52451 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -305,7 +305,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(3):
+    for i in range(10):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:
diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 220885f2..5ac1164d 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -459,7 +459,6 @@ def scoreboard_sim(dut, alusim):
         for i in range(len(dut.int_insn_i)):
             yield dut.int_insn_i[i].eq(0)
         yield
-        yield
 
 
     yield
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 220eee7b..a279c9f6 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -1,9 +1,10 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Cat, Array, Const, Elaboratable
-from nmutil.latch import SRLatch
 from nmigen.lib.coding import Decoder
 
+from nmutil.latch import SRLatch, latchregister
+
 from .shadow_fn import ShadowFn
 
 
@@ -134,16 +135,24 @@ class FnUnit(Elaboratable):
         m.d.comb += rd_l.s.eq(self.issue_i)
         m.d.comb += rd_l.r.eq(self.go_rd_i | recover)
 
-        # dest decoder: write-pending out
-        m.d.comb += dest_d.i.eq(self.dest_i)
+        # latch/registers for dest / src1 / src2
+        dest_r = Signal(max=self.reg_width, reset_less=True)
+        src1_r = Signal(max=self.reg_width, reset_less=True)
+        src2_r = Signal(max=self.reg_width, reset_less=True)
+        latchregister(m, self.dest_i, dest_r, wr_l.qn)
+        latchregister(m, self.src1_i, src1_r, wr_l.qn)
+        latchregister(m, self.src2_i, src2_r, wr_l.qn)
+
+        # dest decoder (use dest reg as input): write-pending out
+        m.d.comb += dest_d.i.eq(dest_r)
         m.d.comb += dest_d.n.eq(wr_l.qn) # decode is inverted
         m.d.comb += self.busy_o.eq(wr_l.q) # busy if set
         m.d.comb += xx_pend_o.eq(dest_d.o)
 
-        # src1/src2 decoder: read-pending out
-        m.d.comb += src1_d.i.eq(self.src1_i)
+        # src1/src2 decoder (use src1/2 regs as input): read-pending out
+        m.d.comb += src1_d.i.eq(src1_r)
         m.d.comb += src1_d.n.eq(rd_l.qn) # decode is inverted
-        m.d.comb += src2_d.i.eq(self.src2_i)
+        m.d.comb += src2_d.i.eq(src2_r)
         m.d.comb += src2_d.n.eq(rd_l.qn) # decode is inverted
         m.d.comb += self.src1_pend_o.eq(src1_d.o)
         m.d.comb += self.src2_pend_o.eq(src2_d.o)