From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 12:25:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2328
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=251cff8f71520e2c9458000af34460a2d3014d3e;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4b392ee00..5aa83bdde 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -587,8 +587,9 @@ cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputi
 has OpenCAPI Memory interfaces, and requires an OMI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
-Extra-V appears to be a remarkable research project that, by leveraging
-OpenCAPI, assuming that the map of edges in any given arbitrary data graph
+Extra-V appears to be a remarkable research project based on OpenCAPI that,
+by assuming that the map of edges (excluding the actual data)
+in any given arbitrary data graph
 could be kept by the main CPU in-memory, could distribute and delegate
 a limited-capability deterministic but most importantly *data-dependent*
 node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier).  A miniature processor