From: Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Date: Tue, 26 Sep 2017 10:33:37 +0000 (+0000)
Subject: S/390: Add support for vec_shr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=252c6f56386b674a6fb9329d928269858a2cfe35;p=gcc.git

S/390: Add support for vec_shr

gcc/ChangeLog:

2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/predicates.md ("const_shift_by_byte_operand"): New
	predicate.
	* config/s390/vector.md ("*vec_srb<mode>"): Change modes to V_128
	and V16QI.
	("*vec_slb<mode>"): New insn pattern.
	("vec_shr_<mode>"): New expander.
	* config/s390/vx-builtins.md ("vec_slb<mode>"): Turn into expander
	and force the shift count operand to V16QImode.
	("vec_srb<mode>"): Set shift count mode to V16QI.

From-SVN: r253193
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9df1ff54470..71339e16b42 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+	* config/s390/predicates.md ("const_shift_by_byte_operand"): New
+	predicate.
+	* config/s390/vector.md ("*vec_srb<mode>"): Change modes to V_128
+	and V16QI.
+	("*vec_slb<mode>"): New insn pattern.
+	("vec_shr_<mode>"): New expander.
+	* config/s390/vx-builtins.md ("vec_slb<mode>"): Turn into expander
+	and force the shift count operand to V16QImode.
+	("vec_srb<mode>"): Set shift count mode to V16QI.
+
 2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
 	* config/s390/vector.md ("vec_widen_umult_lo_<mode>")
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index db966dd6bcb..bbff8d856c2 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -508,3 +508,10 @@
     }
   return true;
 })
+
+(define_predicate "const_shift_by_byte_operand"
+  (match_code "const_int")
+{
+  unsigned HOST_WIDE_INT val = INTVAL (op);
+  return val <= 128 && val % 8 == 0;
+})
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 29131cdbf35..e61bb88a405 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -980,15 +980,43 @@
 
 ; Pattern used by e.g. popcount
 (define_insn "*vec_srb<mode>"
-  [(set (match_operand:V_HW 0 "register_operand"                    "=v")
-	(unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
-		      (match_operand:<tointvec> 2 "register_operand" "v")]
-		     UNSPEC_VEC_SRLB))]
+  [(set (match_operand:V_128                0 "register_operand" "=v")
+	(unspec:V_128 [(match_operand:V_128 1 "register_operand"  "v")
+		       (match_operand:V16QI 2 "register_operand"  "v")]
+		   UNSPEC_VEC_SRLB))]
   "TARGET_VX"
   "vsrlb\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
 
+; Vector shift left by byte
+
+(define_insn "*vec_slb<mode>"
+  [(set (match_operand:V_128                0 "register_operand" "=v")
+	(unspec:V_128 [(match_operand:V_128 1 "register_operand"  "v")
+		    (match_operand:V16QI    2 "register_operand"  "v")]
+		   UNSPEC_VEC_SLB))]
+  "TARGET_VX"
+  "vslb\t%v0,%v1,%v2"
+  [(set_attr "op_type" "VRR")])
+
+; vec_shr is defined as shift towards element 0
+; this means it is a left shift on BE targets!
+(define_expand "vec_shr_<mode>"
+  [(set (match_dup 3)
+	(unspec:V16QI [(match_operand:SI 2 "const_shift_by_byte_operand" "")
+		   (const_int 7)
+		   (match_dup 3)]
+		   UNSPEC_VEC_SET))
+   (set (match_operand:V_128 0 "register_operand" "")
+	(unspec:V_128 [(match_operand:V_128 1 "register_operand" "")
+		    (match_dup 3)]
+		   UNSPEC_VEC_SLB))]
+  "TARGET_VX"
+ {
+   operands[3] = gen_reg_rtx(V16QImode);
+ })
+
 ; vmnb, vmnh, vmnf, vmng
 (define_insn "smin<mode>3"
   [(set (match_operand:VI          0 "register_operand" "=v")
@@ -1779,9 +1807,6 @@
 ; reduc_umin
 ; reduc_umax
 
-; vec_shl vrep + vsl
-; vec_shr
-
 ; vec_pack_sfix_trunc: convert + pack ?
 ; vec_pack_ufix_trunc
 ; vec_unpacks_float_hi
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 54796df041b..4c157e32efb 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -1005,15 +1005,16 @@
 
 ; Vector shift left by byte
 
-(define_insn "vec_slb<mode>"
-  [(set (match_operand:V_HW 0 "register_operand"                    "=v")
-	(unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
-		      (match_operand:<tointvec> 2 "register_operand" "v")]
+; Pattern definition in vector.md, see vec_vslb
+(define_expand "vec_slb<mode>"
+  [(set (match_operand:V_HW 0 "register_operand"                     "")
+	(unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
+		      (match_operand:<tointvec> 2 "register_operand" "")]
 		     UNSPEC_VEC_SLB))]
   "TARGET_VX"
-  "vslb\t%v0,%v1,%v2"
-  [(set_attr "op_type" "VRR")])
-
+{
+  PUT_MODE (operands[2], V16QImode);
+})
 
 ; Vector shift left double by byte
 
@@ -1076,14 +1077,16 @@
 
 ; Vector shift right logical by byte
 
-; Pattern definition in vector.md
+; Pattern definition in vector.md, see vec_vsrb
 (define_expand "vec_srb<mode>"
   [(set (match_operand:V_HW 0 "register_operand"                     "")
 	(unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
 		      (match_operand:<tointvec> 2 "register_operand" "")]
 		     UNSPEC_VEC_SRLB))]
-  "TARGET_VX")
-
+  "TARGET_VX"
+{
+  PUT_MODE (operands[2], V16QImode);
+})
 
 ; Vector subtract