From: Slan <chezslan@gmail.com>
Date: Fri, 22 Jan 2021 09:53:02 +0000 (+0200)
Subject: Fix broken timing constraints
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=255f26cf45361091244631d2c61d7f739f6146da;p=nmigen.git

Fix broken timing constraints
---

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 25bfa28..128035d 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -421,12 +421,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             m.d.async_ff += o.eq(i)
 
         if async_ff_sync._edge == "pos":
-            m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
+            m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i)
         else:
-            m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
+            m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
             async_ff_sync.o.eq(flops[-1])
         ]