From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Oct 2020 16:22:09 +0000 (+0100)
Subject: comment SRR1 mem.exception
X-Git-Tag: 24jan2021_ls180~207
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=256e1c78f0f26215879895509e37ac40a55c25f4;p=soc.git

comment SRR1 mem.exception
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 60a49d4f..ced6e9f5 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -916,11 +916,7 @@ class PowerDecode2(PowerDecodeSubset):
                 with m.If(exc.segment_fault):
                     self.trap(m, TT.PRIV, 0x480)
                 with m.Else():
-                    # TODO
-                    #srr1(63 - 33) <= exc.invalid;
-                    #srr1(63 - 35) <= exc.perm_error; -- noexec fault
-                    #srr1(63 - 44) <= exc.badtree;
-                    #srr1(63 - 45) <= exc.rc_error;
+                    #spass exception info to trap to create SRR1
                     self.trap(m, TT.MEMEXC, 0x400, exc)
             with m.Else():
                 with m.If(exc.segment_fault):