From: lkcl Date: Wed, 30 Dec 2020 17:20:21 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~700 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=256f601e0a6f3ad42c724e793c4839fb98e9c998;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 08cb3b54f..b87cecdfc 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -144,12 +144,12 @@ this is where our "simple" loop gets its first complexity. if (RA.isvec) { irs1 += 1; } if (RB.isvec) { irs2 += 1; } -This could have been written out as eight separate cases: one each for when each of RA, RB or RT is scalar or vector. Those eight cases, when optimally combined, result in the pseudocode above. +This could have been written out as eight separate cases: one each for when each of `RA`, `RB` or `RT` is scalar or vector. Those eight cases, when optimally combined, result in the pseudocode above. With some walkthroughs it is clear that the loop exits immediately after the first scalar destination result is written, and that when the destination is a Vector the loop proceeds to fill up the register file, -sequentially, starting at `rd` and ending at `rd+VL-1`. The two source +sequentially, starting at `RT` and ending at `RT+VL-1`. The two source registers will, independently, either remain pointing at `RB` or `RA` respectively, or, if marked as Vectors, will march incrementally in lockstep, producing element results along the way, as the destination