From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 19:30:54 +0000 (-0700)
Subject: When creating new holes cell, inherit parameters too
X-Git-Tag: working-ls180~1208^2~218
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=257f7ff5f63635f0a754f34cf8af93ed06632b5b;p=yosys.git

When creating new holes cell, inherit parameters too
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 90fea2db1..818caebba 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -796,8 +796,10 @@ struct XAigerWriter
 				RTLIL::Module* box_module = module->design->module(cell->type);
 				int box_inputs = 0, box_outputs = 0;
 				Cell *holes_cell = nullptr;
-				if (box_module->get_bool_attribute("\\whitebox"))
+				if (box_module->get_bool_attribute("\\whitebox")) {
 					holes_cell = holes_module->addCell(cell->name, cell->type);
+					holes_cell->parameters = cell->parameters;
+				}
 
 				// NB: Assume box_module->ports are sorted alphabetically
 				//     (as RTLIL::Module::fixup_ports() would do)