From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 7 May 2022 18:30:51 +0000 (+0000)
Subject: ppc/svp64: support setvl instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2582c097e95385dfbc230de5d39aaf3a91a570ea;p=binutils-gdb.git

ppc/svp64: support setvl instructions

https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
---

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a2e23a2c6af..cd4dd658ce5 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -153,3 +153,5 @@ run_dump_test "rop-checks"
 run_dump_test "dcbt"
 run_dump_test "pr27676"
 run_dump_test "raw"
+
+run_dump_test "setvl"
diff --git a/gas/testsuite/gas/ppc/setvl.d b/gas/testsuite/gas/ppc/setvl.d
new file mode 100644
index 00000000000..a241c64fd16
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.d
@@ -0,0 +1,15 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:	(37 00 00 58|58 00 00 37) 	setvl.  r0,r0,1,0,0,0
+.*:	(36 00 00 58|58 00 00 36) 	setvl   r0,r0,1,0,0,0
+.*:	(36 00 e0 5b|5b e0 00 36) 	setvl   r31,r0,1,0,0,0
+.*:	(36 00 1f 58|58 1f 00 36) 	setvl   r0,r31,1,0,0,0
+.*:	(36 7e 00 58|58 00 7e 36) 	setvl   r0,r0,64,0,0,0
+.*:	(76 00 00 58|58 00 00 76) 	setvl   r0,r0,1,1,0,0
+.*:	(b6 00 00 58|58 00 00 b6) 	setvl   r0,r0,1,0,1,0
diff --git a/gas/testsuite/gas/ppc/setvl.s b/gas/testsuite/gas/ppc/setvl.s
new file mode 100644
index 00000000000..b7f1825b54b
--- /dev/null
+++ b/gas/testsuite/gas/ppc/setvl.s
@@ -0,0 +1,7 @@
+setvl. 0,0,1,0,0,0
+setvl 0,0,1,0,0,0
+setvl 31,0,1,0,0,0
+setvl 0,31,1,0,0,0
+setvl 0,0,64,0,0,0
+setvl 0,0,1,1,0,0
+setvl 0,0,1,0,1,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index fe2fcaeb1d3..90f813a2807 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2719,6 +2719,7 @@ extract_thds (uint64_t insn,
 
   return value;
 }
+
 
 /* The operands table.
 
@@ -3825,6 +3826,18 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define HH DDD + 1
   { 0x3, 13, NULL, NULL, 0 },
+
+#define SVi HH + 1
+  { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
+
+#define vf SVi + 1
+  { 0x1, 6, NULL, NULL, 0 },
+
+#define vs vf + 1
+  { 0x1, 7, NULL, NULL, 0 },
+
+#define ms vs + 1
+  { 0x1, 8, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -4694,6 +4707,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 #define APU_RT_MASK (APU_MASK | RT_MASK)
 #define APU_RA_MASK (APU_MASK | RA_MASK)
 
+/* An SVL form instruction. */
+#define SVL(op, xop, rc)			\
+  (OP (op)					\
+   | ((((uint64_t)(xop)) & 0x1f) << 1)		\
+   | (((uint64_t)(rc)) & 1))
+#define SVL_MASK	SVL (0x3f, 0x1f, 1)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -6763,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"rlmi",	M(22,0),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 {"rlmi.",	M(22,1),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 
+{"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
+{"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
+
 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
 {"rlwnm",	M(23,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 {"rlnm",	M(23,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},