From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 3 Apr 2015 11:57:37 +0000 (+0200)
Subject: soc/cpuif: fix CSR base generation for memories (name is already fullname)
X-Git-Tag: 24jan2021_ls180~2396
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2583e975f005e5f74f068ce908e78085804ca9d6;p=litex.git

soc/cpuif: fix CSR base generation for memories (name is already fullname)
---

diff --git a/misoclib/soc/cpuif.py b/misoclib/soc/cpuif.py
index be58bd8d..737d2c71 100644
--- a/misoclib/soc/cpuif.py
+++ b/misoclib/soc/cpuif.py
@@ -72,8 +72,7 @@ def get_csr_header(regions, interrupt_map):
 	r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
 	for name, origin, busword, obj in regions:
 		if isinstance(obj, Memory):
-			fullname = name + "_" + obj.name_override
-			r += "#define CSR_"+fullname.upper()+"_BASE "+hex(origin)+"\n"
+			r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n"
 		else:
 			r += "\n/* "+name+" */\n"
 			r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n"