From: Bobby R. Bruce <bbruce@ucdavis.edu>
Date: Wed, 3 Feb 2021 19:48:51 +0000 (-0800)
Subject: misc: Merge branch v20.1.0.3 hotfix into develop
X-Git-Tag: develop-gem5-snapshot~147^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=258a5cb55356d4d85f0ce2bdfeaeaf47bfc08fa4;p=gem5.git

misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d
---

258a5cb55356d4d85f0ce2bdfeaeaf47bfc08fa4
diff --cc src/arch/arm/ArmISA.py
index bc5f82378,072572689..59d3919d5
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@@ -113,11 -108,10 +113,11 @@@ class ArmISA(BaseISA)
      # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
      id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
          "AArch64 Memory Model Feature Register 0")
-     # PAN | HPDS | VHE
-     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101100,
+     # PAN | HPDS | !VHE
+     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
          "AArch64 Memory Model Feature Register 1")
 -    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 +    # |VARANGE
 +    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,
          "AArch64 Memory Model Feature Register 2")
  
      # Any access (read/write) to an unimplemented
diff --cc src/arch/arm/isa.cc
index f4fabc16a,8adbdabdb..2429e5cb0
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@@ -100,9 -101,10 +101,10 @@@ ISA::ISA(const Params &p) : BaseISA(p)
          haveLargeAsid64 = false;
          physAddrRange = 32;  // dummy value
          haveSVE = true;
+         haveVHE = false;
          havePAN = false;
          haveSecEL2 = true;
 -        sveVL = p->sve_vl_se;
 +        sveVL = p.sve_vl_se;
          haveLSE = true;
          haveTME = true;
      }
diff --cc src/arch/arm/system.cc
index 7f5fa1313,0bbc701e9..783366dd3
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@@ -63,22 -64,23 +63,23 @@@ ArmSystem::ArmSystem(const Params &p
        _genericTimer(nullptr),
        _gic(nullptr),
        _pwrCtrl(nullptr),
 -      _highestELIs64(p->highest_el_is_64),
 -      _physAddrRange64(p->phys_addr_range_64),
 -      _haveLargeAsid64(p->have_large_asid_64),
 -      _haveTME(p->have_tme),
 -      _haveSVE(p->have_sve),
 -      _sveVL(p->sve_vl),
 -      _haveLSE(p->have_lse),
 -      _haveVHE(p->have_vhe),
 -      _havePAN(p->have_pan),
 -      _haveSecEL2(p->have_secel2),
 -      semihosting(p->semihosting),
 -      multiProc(p->multi_proc)
 -{
 -      if (p->auto_reset_addr) {
 +      _highestELIs64(p.highest_el_is_64),
 +      _physAddrRange64(p.phys_addr_range_64),
 +      _haveLargeAsid64(p.have_large_asid_64),
 +      _haveTME(p.have_tme),
 +      _haveSVE(p.have_sve),
 +      _sveVL(p.sve_vl),
 +      _haveLSE(p.have_lse),
++      _haveVHE(p.have_vhe),
 +      _havePAN(p.have_pan),
 +      _haveSecEL2(p.have_secel2),
 +      semihosting(p.semihosting),
 +      multiProc(p.multi_proc)
 +{
 +    if (p.auto_reset_addr) {
          _resetAddr = workload->getEntry();
      } else {
 -        _resetAddr = p->reset_addr;
 +        _resetAddr = p.reset_addr;
          warn_if(workload->getEntry() != _resetAddr,
                  "Workload entry point %#x and reset address %#x are different",
                  workload->getEntry(), _resetAddr);