From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 15:27:01 +0000 (+0100)
Subject: code comments
X-Git-Tag: div_pipeline~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25a05f91d67aedb5453e2f614d41e7b3cf0affcb;p=soc.git

code comments
---

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index fdbe8659..32f29e68 100644
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -27,10 +27,12 @@ class DivCoreBaseStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()
 
+        # pass-through on non-core parameters
         m.d.comb += self.o.eq_without_core(self.i)
 
         m.submodules.core = self.core
 
+        # copy parameters to/from divremsqrt core into the Base, here.
         m.d.comb += self.core.i.eq(self.i.core)
         m.d.comb += self.o.core.eq(self.core.o)