From: Nils Asmussen <nils.asmussen@barkhauseninstitut.org>
Date: Mon, 24 Feb 2020 12:45:22 +0000 (+0100)
Subject: arch-riscv: print information about faults.
X-Git-Tag: v20.0.0.0~256
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25a538ff20de23abb8d7eb2f959d6d333c110cb9;p=gem5.git

arch-riscv: print information about faults.

Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25646
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
---

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 1d48d85db..2296992f2 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -2,6 +2,7 @@
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,6 +37,7 @@
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Fault.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"
 
@@ -53,6 +55,9 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     PCState pcState = tc->pcState();
 
+    DPRINTFS(Fault, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
+             name(), pcState);
+
     if (FullSystem) {
         PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
         PrivilegeMode prv = PRV_M;