From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 6 Mar 2019 21:46:01 +0000 (+0000)
Subject: add some comments to FPAddBase
X-Git-Tag: ls180-24jan2020~1721
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25a892466594952291f03b50c5daf29a1335c11f;p=ieee754fpu.git

add some comments to FPAddBase
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 2f5d9811..fcedea6a 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -1182,11 +1182,14 @@ class FPADD(FPID):
            |
         FPGetOp (b)
            |
-        FPAddBase---> GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
-           |
-        PutZ
+        FPAddBase---> FPAddBaseMod
+           |            |
+        PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
 
         FPAddBase is tricky: it is both a stage and *has* stages.
+        Connection to FPAddBaseMod therefore requires an in stb/ack
+        and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
+        needs to be the thing that raises the incoming stb.
     """
 
     def __init__(self, width, id_wid=None, single_cycle=False):