From: Luke Kenneth Casson Leighton Date: Tue, 11 Aug 2020 12:17:18 +0000 (+0100) Subject: whoops fix change of variable (state) msr/pc X-Git-Tag: semi_working_ecp5~403 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25aa7daa19229984e8bc34b291ab60bf4a658b96;p=soc.git whoops fix change of variable (state) msr/pc --- diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index b7ea7b4e..5ec59766 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -224,8 +224,8 @@ class TestRunner(unittest.TestCase): # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(bigendian) # little / big? - yield pdecode2.msr.eq(msr) # set MSR in pdecode2 - yield pdecode2.cia.eq(pc) # set CIA in pdecode2 + yield pdecode2.state.msr.eq(msr) # set MSR in pdecode2 + yield pdecode2.state.pc.eq(pc) # set CIA in pdecode2 yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.do.fn_unit