From: Vladimir Makarov Date: Fri, 8 Feb 2013 21:59:11 +0000 (+0000) Subject: re PR rtl-optimization/56246 (ICE in assign_by_spills, at lra-assigns.c:1262) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25bb0bb5b0d6f5b0e23cd20f77cbddfcb41ca92a;p=gcc.git re PR rtl-optimization/56246 (ICE in assign_by_spills, at lra-assigns.c:1262) 2013-02-08 Vladimir Makarov PR rtl-optimization/56246 * lra-constraints.c (simplify_operand_subreg): Try tor reuse reload pseudo. * lra.c (lra): Clear lra_optional_reload_pseudos only when all constraints are satisfied. 2013-02-08 Vladimir Makarov PR rtl-optimization/56246 * gcc.target/i386/pr56246.c: New test. From-SVN: r195902 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2693b7e843e..1b24e789154 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-02-08 Vladimir Makarov + + PR rtl-optimization/56246 + * lra-constraints.c (simplify_operand_subreg): Try tor reuse + reload pseudo. + * lra.c (lra): Clear lra_optional_reload_pseudos only when all + constraints are satisfied. + 2013-02-08 Jeff Law PR debug/53948 diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 13420ebfbd8..49c9723fc48 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -1213,24 +1213,26 @@ simplify_operand_subreg (int nop, enum machine_mode reg_mode) enum reg_class rclass = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); - new_reg = lra_create_new_reg_with_unique_value (reg_mode, reg, rclass, - "subreg reg"); - bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (new_reg)); - if (type != OP_OUT - || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode)) + if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, + rclass, "subreg reg", &new_reg)) { - push_to_sequence (before); - lra_emit_move (new_reg, reg); - before = get_insns (); - end_sequence (); - } - if (type != OP_IN) - { - start_sequence (); - lra_emit_move (reg, new_reg); - emit_insn (after); - after = get_insns (); - end_sequence (); + bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (new_reg)); + if (type != OP_OUT + || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode)) + { + push_to_sequence (before); + lra_emit_move (new_reg, reg); + before = get_insns (); + end_sequence (); + } + if (type != OP_IN) + { + start_sequence (); + lra_emit_move (reg, new_reg); + emit_insn (after); + after = get_insns (); + end_sequence (); + } } SUBREG_REG (operand) = new_reg; lra_process_new_insns (curr_insn, before, after, diff --git a/gcc/lra.c b/gcc/lra.c index 6271660d8ab..875c7afddab 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -2272,7 +2272,6 @@ lra (FILE *f) { for (;;) { - bitmap_clear (&lra_optional_reload_pseudos); /* We should try to assign hard registers to scratches even if there were no RTL transformations in lra_constraints. */ @@ -2311,6 +2310,7 @@ lra (FILE *f) live_p = false; } } + bitmap_clear (&lra_optional_reload_pseudos); bitmap_clear (&lra_inheritance_pseudos); bitmap_clear (&lra_split_regs); if (! lra_need_for_spills_p ()) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 83843b76581..56299003f67 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-02-08 Vladimir Makarov + + PR rtl-optimization/56246 + * gcc.target/i386/pr56246.c: New test. + 2013-02-08 Jeff Law PR debug/53948 diff --git a/gcc/testsuite/gcc.target/i386/pr56246.c b/gcc/testsuite/gcc.target/i386/pr56246.c new file mode 100644 index 00000000000..64a2527a549 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr56246.c @@ -0,0 +1,7 @@ +/* PR target/56225 */ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -fno-omit-frame-pointer -march=i686 -fpic" } */ + +void NoBarrier_AtomicExchange (long long *ptr) { + while (__sync_val_compare_and_swap (ptr, 1, 0) ); +}