From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Feb 2021 19:27:06 +0000 (+0000)
Subject: err trying to put in some FSM handshake signals, getting confused
X-Git-Tag: convert-csv-opcode-to-binary~171
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25c06d8bc4e186acce63e69d0c3213da6f97da9c;p=soc.git

err trying to put in some FSM handshake signals, getting confused
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 68ecbff5..62406514 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -434,11 +434,16 @@ class TestIssuerInternal(Elaboratable):
         # these are the handshake signals between fetch and decode/execute
 
         # fetch FSM can run as soon as the PC is valid
-        fetch_pc_valid_i = Signal()
-        fetch_pc_ready_o = Signal()
+        fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
+        fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
+
+        # SVSTATE FSM TODO.
+        svloop_ready_i = Signal()
+        svloop_valid_o = Signal()
+
         # when done, deliver the instruction to the next FSM
-        fetch_insn_valid_o = Signal()
-        fetch_insn_ready_i = Signal()
+        fetch_insn_valid_o = Signal() 
+        fetch_insn_ready_i = Signal() # Execute acknowledges SVSTATE
 
         # latches copy of raw fetched instruction
         fetch_insn_o = Signal(32, reset_less=True)