From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 3 May 2022 16:40:29 +0000 (+0000)
Subject: ppc/svp64: support LibreSOC architecture
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25dd7a2f56e8e44258be4df6daa22ca354c9da88;p=binutils-gdb.git
ppc/svp64: support LibreSOC architecture
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
---
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 4d789fd16a9..76bdfb2e351 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\
+-mlibresoc generate code for Libre-SOC architecture\n"));
+ fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e1..d5752a42e67 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 45e8faeef5e..f61e6518f14 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "libresoc", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5bd6dac50f..fe2fcaeb1d3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4826,6 +4826,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP
+#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW