From: Robert Jordens <jordens@gmail.com>
Date: Sun, 5 Apr 2015 09:49:07 +0000 (-0600)
Subject: decorators: remove deprecated semantics
X-Git-Tag: 24jan2021_ls180~2099^2~123
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25e4d2a2db43ed8e62aa6b3dffc5e3e5ff14aeb3;p=litex.git

decorators: remove deprecated semantics
---

diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 72352204..79519d4a 100644
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -2,8 +2,8 @@ from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Example(Module):
 	def __init__(self, width):
 		d1 = divider.Divider(width)
diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 4a044b8f..548c3add 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -158,7 +158,7 @@ class AsyncFIFO(Module, _FIFOInterface):
 	"""Asynchronous FIFO (first in, first out)
 
 	Read and write interfaces are accessed from different clock domains,
-	named `read` and `write`. Use `RenameClockDomains` to rename to
+	named `read` and `write`. Use `ClockDomainsRenamer` to rename to
 	other names.
 
 	{interface}
@@ -172,8 +172,8 @@ class AsyncFIFO(Module, _FIFOInterface):
 
 		depth_bits = log2_int(depth, True)
 
-		produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
-		consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
+		produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
+		consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
 		self.submodules += produce, consume
 		self.comb += [
 			produce.ce.eq(self.writable & self.we),
diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
index 8942ab0b..b505032e 100644
--- a/migen/genlib/misc.py
+++ b/migen/genlib/misc.py
@@ -86,24 +86,24 @@ def timeline(trigger, events):
 	sync.append(counterlogic)
 	return sync
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class FlipFlop(Module):
 	def __init__(self, *args, **kwargs):
 		self.d = Signal(*args, **kwargs)
 		self.q = Signal(*args, **kwargs)
 		self.sync += self.q.eq(self.d)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Counter(Module):
 	def __init__(self, *args, increment=1, **kwargs):
 		self.value = Signal(*args, **kwargs)
 		self.width = flen(self.value)
 		self.sync += self.value.eq(self.value+increment)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Timeout(Module):
 	def __init__(self, length):
 		self.reached = Signal()