From: lkcl <lkcl@web>
Date: Mon, 3 Apr 2023 23:51:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25e54c4c037207cc65394503b3dd4cccd1fa8468;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 0851e021e..5d51e3481 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -1122,13 +1122,14 @@ that is offset by MAXVL, both halves actually starting from RT.
 If VL is 3, MAXVL is 5, RT is 1, and dest elwidth is 32 then the elements
 RT0 to RT2 are stored:
 
-          0..31     32..63
-     r0  unchanged unchanged
-     r1  RT0.lo    RT1.lo
-     r2  RT2.lo    unchanged
-     r3  unchanged RT0.hi
-     r4  RT1.hi    RT2.hi
-     r5  unchanged unchanged
+     LSB0:  63:32     31:0
+     MSB0:  0:31      32:63
+     r0    unchanged unchanged
+     r1    RT1.lo    RT0.lo
+     r2    unchanged RT2.lo
+     r3    RT0.hi    unchanged
+     r4    RT2.hi    RT1.hi
+     r5    unchanged unchanged
 
 Note that all of the LO halves start from r1, but that the HI halves
 start from half-way into r3. The reason is that with MAXVL bring