From: lkcl <lkcl@web>
Date: Fri, 19 Aug 2022 04:36:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~833
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25e5ceb3a2ec4308c5437acb563cbaa691459d2f;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 312b4abb9..852b6b18e 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -602,7 +602,8 @@ multiplied by zero.  Thus, a sequence of LD operations will load from
 the exact same address, and likewise STs to the exact same address.
 
 Ordinarily this would make absolutely no sense whatsoever, except
-that Power ISA has cache-inhibited LD/STs, for accessing memory-mapped
+that Power ISA has cache-inhibited LD/STs (Power ISA v.1, Book III,
+1.6.1, p1033), for accessing memory-mapped
 peripherals and other crucial uses.  Thus, *despite not being a mapreduce mode*,
 zero-immediates cause multiple hits on the same element.