From: whitequark Date: Sat, 11 Dec 2021 11:12:25 +0000 (+0000) Subject: sim.pysim: refuse to write VCD files with whitespace in signal names. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25fb949a9b41eb8dd66d493b7c393e54d62f09a4;p=nmigen.git sim.pysim: refuse to write VCD files with whitespace in signal names. Closes #595. --- diff --git a/nmigen/sim/pysim.py b/nmigen/sim/pysim.py index ec98fb0..0d8b659 100644 --- a/nmigen/sim/pysim.py +++ b/nmigen/sim/pysim.py @@ -1,5 +1,6 @@ from contextlib import contextmanager import itertools +import re from vcd import VCDWriter from vcd.gtkw import GTKWSave @@ -94,6 +95,10 @@ class _VCDWriter: var_init = signal.reset for (*var_scope, var_name) in names: + if re.search(r"[ \t\r\n]", var_name): + raise NameError("Signal '{}.{}' contains a whitespace character" + .format(".".join(var_scope), var_name)) + suffix = None while True: try: diff --git a/tests/test_sim.py b/tests/test_sim.py index a64e90f..8d29bfb 100644 --- a/tests/test_sim.py +++ b/tests/test_sim.py @@ -806,8 +806,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase): sim.run_until(1e-5) with self.assertRaisesRegex(ValueError, r"^Cannot start writing waveforms after advancing simulation time$"): - with sim.write_vcd(open(os.path.devnull, "wt")): - pass + with open(os.path.devnull, "w") as f: + with sim.write_vcd(f): + pass class SimulatorRegressionTestCase(FHDLTestCase): @@ -827,3 +828,15 @@ class SimulatorRegressionTestCase(FHDLTestCase): self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1) sim.add_process(process) sim.run() + + def test_bug_595(self): + dut = Module() + with dut.FSM(name="name with space"): + with dut.State(0): + pass + sim = Simulator(dut) + with self.assertRaisesRegex(NameError, + r"^Signal 'top\.name with space_state' contains a whitespace character$"): + with open(os.path.devnull, "w") as f: + with sim.write_vcd(f): + sim.run()