From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 May 2020 18:26:25 +0000 (+0100)
Subject: add debug info of what instruction was executed and Asserted
X-Git-Tag: div_pipeline~1127
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=25fddab0a77fae96986a0d75f6bbe9ad65060476;p=soc.git

add debug info of what instruction was executed and Asserted
---

diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py
index ccb41a76..ef90ddca 100644
--- a/src/soc/cr/test/test_pipe_caller.py
+++ b/src/soc/cr/test/test_pipe_caller.py
@@ -186,6 +186,7 @@ class TestRunner(FHDLTestCase):
                         cr_expected = simulator.cr.get_range().value
                         cr_real = yield alu.n.data_o.cr
                         msg = f"real: {cr_expected:x}, actual: {cr_real:x}"
+                        msg += " code: %s" % code
                         self.assertEqual(cr_expected, cr_real, msg)
 
         sim.add_sync_process(process)