From: whitequark <cz@m-labs.hk>
Date: Thu, 13 Dec 2018 18:17:58 +0000 (+0000)
Subject: back.pysim: fix handling of process termination.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=261243e25ea27e89368c0f87e03db91977d6f9ac;p=nmigen.git

back.pysim: fix handling of process termination.
---

diff --git a/examples/ctrl.py b/examples/ctrl.py
index 17a9e94..4d33e26 100644
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -1,5 +1,5 @@
 from nmigen.fhdl import *
-from nmigen.back import rtlil, verilog
+from nmigen.back import rtlil, verilog, pysim
 
 
 class ClockDivisor:
@@ -17,5 +17,16 @@ class ClockDivisor:
 
 ctr  = ClockDivisor(factor=16)
 frag = ctr.get_fragment(platform=None)
+
 # print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
 print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
+
+sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
+sim.add_clock("sync", 1e-6)
+def sim_proc():
+    yield pysim.Delay(15.25e-6)
+    yield ctr.ce.eq(Const(1))
+    yield pysim.Delay(15e-6)
+    yield ctr.ce.eq(Const(0))
+sim.add_process(sim_proc())
+with sim: sim.run_until(100e-6, run_passive=True)
diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 2afffab..fc298cf 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -320,8 +320,7 @@ class Simulator:
             stmt = proc.send(None)
         except StopIteration:
             self._processes.remove(proc)
-            self._passive.remove(proc)
-            self._suspended.remove(proc)
+            self._passive.discard(proc)
             return
 
         if isinstance(stmt, Delay):