From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Jan 2015 00:30:01 +0000 (+0100)
Subject: add hack to generate verilog with AsyncResetSynchronizer (FIXME)
X-Git-Tag: 24jan2021_ls180~2575^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=261469814ff372f75901efcb7fdde378fe3166ad;p=litex.git

add hack to generate verilog with AsyncResetSynchronizer (FIXME)
---

diff --git a/litesata-version.txt b/litesata-version.txt
deleted file mode 100644
index eba33402..00000000
--- a/litesata-version.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-0.9.0
-
diff --git a/litescope-version.txt b/litescope-version.txt
new file mode 100644
index 00000000..eba33402
--- /dev/null
+++ b/litescope-version.txt
@@ -0,0 +1,2 @@
+0.9.0
+
diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py
index a69f749f..7264bfe0 100644
--- a/litescope/frontend/la.py
+++ b/litescope/frontend/la.py
@@ -1,4 +1,6 @@
 from migen.fhdl.std import *
+from migen.fhdl.specials import Special
+from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.fhdl import verilog
 from migen.bank.description import *
 from migen.actorlib.fifo import AsyncFIFO
@@ -84,7 +86,25 @@ class LiteScopeLA(Module, AutoCSR):
 			self.comb += sink.connect(recorder.dat_sink)
 
 	def export(self, design, layout, filename):
-		ret, ns = verilog.convert(design, return_ns=True)
+		# XXX FIXME
+		class SimAsyncResetSynchronizer(Special):
+			def __init__(self, cd, async_reset):
+				Special.__init__(self)
+				self.cd = cd
+				self.async_reset = async_reset
+
+			def iter_expressions(self):
+				yield self.cd, "clk", SPECIAL_INPUT
+				yield self.cd, "rst", SPECIAL_OUTPUT
+				yield self, "async_reset", SPECIAL_INPUT
+
+			@staticmethod
+			def lower(dr):
+				return Module()
+		so = {
+			AsyncResetSynchronizer:	SimAsyncResetSynchronizer
+		}
+		ret, ns = verilog.convert(design, return_ns=True, special_overrides=so)
 		r = ""
 		def format_line(*args):
 			return ",".join(args) + "\n"
diff --git a/make.py b/make.py
index 987f450e..6abafd75 100644
--- a/make.py
+++ b/make.py
@@ -21,7 +21,7 @@ def _get_args():
 		description="""\
 LiteScope - based on Migen.
 
-This program builds and/or loads LiteSATA components.
+This program builds and/or loads LiteScope components.
 One or several actions can be specified:
 
 clean           delete previous build(s).