From: Claudiu Zissulescu Date: Tue, 25 Feb 2020 08:27:07 +0000 (+0200) Subject: [ARC][committed] Update int_vector_base aux register. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=265b467340e5334a682e47a0e1b69a80c4428349;p=binutils-gdb.git [ARC][committed] Update int_vector_base aux register. INT_VECTOR_BASE auxiliary register is available across all ARC architectures. xxxx-xx-xx Claudiu Zissulescu * arc-regs.h (int_vector_base): Make it available for all ARC CPUs. Signed-off-by: Claudiu Zissulescu --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 73091b9e61d..5d835786418 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-02-25 Claudiu Zissulescu + + * arc-regs.h (int_vector_base): Make it available for all ARC + CPUs. + 2020-02-20 Nelson Chu * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h index a1d98bf1794..4494a0630a1 100644 --- a/opcodes/arc-regs.h +++ b/opcodes/arc-regs.h @@ -71,8 +71,7 @@ DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0) DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0) DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0) DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport) -DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base) -DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base) +DEF (0x25, ARC_OPCODE_ARCALL, NONE, int_vector_base) DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode) DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0) DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1)