From: Tobias Platen <tplaten@posteo.de>
Date: Tue, 6 Oct 2020 19:31:14 +0000 (+0200)
Subject: remove redunant signals
X-Git-Tag: 24jan2021_ls180~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=265c4416bb003060b5839dd746c6574ad6f26c54;p=soc.git

remove redunant signals
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 09d13829..664ee817 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -121,18 +121,7 @@ class PortInterface(RecordObject):
 
         # mmu
         self.mmu_done          = Signal() # keep for now
-        self.mmu_err           = Signal() # XXX remove: already in LDSTException
-        self.mmu_invalid       = Signal() # XXX remove: already in LDSTException
-        # radix tree is invalid
-        self.mmu_badtree       = Signal() # XXX remove: already in LDSTException
-        # segment_check fails
-        self.mmu_segerr        = Signal() # XXX remove: already in LDSTException
-        # permission error takes precedence over RC error
-        self.mmu_perm_error    = Signal() # XXX remove: already in LDSTException
-        self.mmu_rc_error      = Signal() # XXX remove: already in LDSTException
-        # r.prtbl or r.pid
-        self.mmu_sprval        = Signal(64) # XXX remove: not needed
-
+       
         # dcache
         self.ldst_error        = Signal()
         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure