From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Mar 2023 13:43:30 +0000 (+0000)
Subject: add wording for binlut crbinlut to ls007
X-Git-Tag: opf_rfc_ls001_v3~135
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2672abf1129c6470d519ac82c4e91a8552855690;p=libreriscv.git

add wording for binlut crbinlut to ls007
https://bugs.libre-soc.org/show_bug.cgi?id=1017
---

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index ea08f6faa..3f6a4129c 100644
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -220,18 +220,14 @@ CRB-form
 
 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form     |
 |----|----|----|-----|-----|-----|-----|-----|---|----------|
-| NN | BF | msk|BFA  | msk | BFB | TLI | XO  |TLI| CRB-Form |
-
-| 0.5| 6-8 | 9-11 | 12-14 | 15-17 | 18-20 | 21-28 | 29-30 | 31  |
-|----|-----|------|-------|-------|-------|-------|-------|-----|
-| PO | BF  | BFA  | BFB   | BFC   | msk   |  TLI  |  XO   | msk |
+| PO | BF | msk|BFA  | msk | BFB | TLI | XO  |TLI| CRB-Form |
 
 Pseudocode:
 
 ```
-a <- CR[4*BF+32:4*BFA+35]
-b <- CR[4*BFA+32:4*BFB+35]
-c <- CR[4*BFB+32:4*BFC+35]
+a <- CR[4*BF+32:4*BF+35]
+b <- CR[4*BFA+32:4*BFA+35]
+c <- CR[4*BFB+32:4*BFB+35]
 ternary <- (~a & ~b & ~c & TLI[0]*4) | # 4 copies of TLI[0]
            (~a & ~b &  c & TLI[1]*4) | # 4 copies of TLI[1]
            (~a &  b & ~c & TLI[2]*4) | # ...
@@ -286,26 +282,37 @@ Add this section to Book I 3.3.13
 Pseudocode:
 
 ```
-if nh = 1 then
-    lut <- (RC)[56:59]
-else
-    lut <- (RC)[60:63]
-do i = 0 to 63
-    idx <- (RB)[i] || (RA)[i]  # compute index from current bits
-    result[i] <- lut[3 - idx]  # subtract from 3 to index in LSB0 order
+if nh = 1 then lut <- (RC)[56:59]
+else           lut <- (RC)[60:63]
+result <- (~RA & ~RB & lut[0]*64) |
+          (~RA &  RB & lut[1]*64) |
+          ( RA & ~RB & lut[2]*64) |
+          ( RA &  RB & lut[3]*64))
 RT <- result
 ```
 
+For each integer value i, 0 to 63, do the following.
+
+    If nh contains a 0, let lut be the four LSBs of RC
+    (bits 60 to 63).  Otherwise let lut be the next
+    four LSBs of RC (bits 56 to 59).
+
+    Let j be the value of the concatenation of the
+    contents of bit i of RT with bit i of RB.
+
+    The value of bit j of lut is placed into bit i of RT.
+
 Special registers altered:
 
 ```
 None
 ```
 
-**Programming Note**:
+**Programmer's Note**:
 
-Dynamic Ternary Logic may be emulated by appropriate combination of `binlog` and `ternlogi`,
-using the `nh` (next half) operand to select first and second nibble:
+Dynamic Ternary Logic may be emulated by appropriate combination of
+`binlog` and `ternlogi`, using the `nh` (next half) operand to select
+first and second nibble:
 
 ```
 # compute r3 = ternlog(r4, r5, r6, table=r7)
@@ -326,18 +333,33 @@ ternlogi r3, r4, r6, 0b11011000
 With ternary (LUT3) dynamic instructions being very costly,
 and CR Fields being only 4 bit, a binary (LUT2) variant is better
 
-| 0.5|6.8 | 9.11|12.14|15.17|18.21|22...30  |31|
-| -- | -- | --- | --- | --- |-----| -------- |--|
-| NN | BT | BA  | BB  | BC  |m0-m3|000101110 |0 |
+| 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form     |
+|----|----|----|-----|-----|-----|-----|-----|---|----------|
+| PO | BF | msk|BFA  | msk | BFB | //  | XO  |// | CRB-Form |
+
+```
+a <- CR[4*BF+32:4*BFA+35]
+b <- CR[4*BFA+32:4*BFA+35]
+lut <- CR[4*BFB+32:4*BFB+35]
+binary <- (~a & ~b & lut[0]*4) |
+          (~a &  b & lut[1]*4) |
+          ( a & ~b & lut[2]*4) |
+          ( a &  b & lut[3]*4))
+do i = 0 to 3
+    if msk[i] = 1 then
+        CR[4*BF+32+i] <- binary[i]
+```
 
-    mask = m0..m3
-    for i in range(4):
-        a,b = CRs[BA][i], CRs[BB][i])
-        if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
+For each integer value i, 0 to 3, do the following.
 
-When SVP64 Vectorised any of the 4 operands may be Scalar or
-Vector, including `BC` meaning that multiple different dynamic
-lookups may be performed with a single instruction.
+    Let j be the value of the concatenation of the
+    contents of bit i of CR Field BF with bit i of CR Field BFA.
+
+    If bit i of msk is set to 1 then the value of bit j of
+    CR Field BFB is placed into bit i of CR Field BF.
+
+    Otherwise, if bit i of msk is a zero then bit i of
+    CR Field BF is unchanged.
 
 *Programmer's note: just as with binlut and ternlogi, a pair
  of crbinlog instructions followed by a merging crternlogi may
@@ -357,9 +379,12 @@ lookups may be performed with a single instruction.
     Appendix G Power ISA sorted by Compliancy Subset
     Appendix H Power ISA sorted by mnemonic
 
-|Form| Book | Page | Version | mnemonic | Description |
-|----|------|------|---------|----------|-------------|
-|TLI | I    | #    | 3.2B    | ternlogi | Ternary Logic Immediate |
+|Form| Book | Page | Version | mnemonic   | Description |
+|----|------|------|---------|------------|-------------|
+|TLI | I    | #    | 3.2B    | ternlogi   | GPR Ternary Logic Immediate |
+|VA  | I    | #    | 3.2B    | binlog     | GPR Binary Logic            |
+|CRB | I    | #    | 3.2B    | crternlogi | CR Field Ternary Logic Immediate |
+|CRB | I    | #    | 3.2B    | crbinlog   | CR Field Binary Logic |
 
 ----------------