From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Dec 2021 02:44:57 +0000 (+0000)
Subject: whoops, use MSR.IR for I-Cache fetch!
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2674696760ff3d1b8981120f9a7eaa258550ae96;p=soc.git

whoops, use MSR.IR for I-Cache fetch!
virtual memory instruction fetch uses MSR.IR not MSR.DR
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ffb7dc97..ab414f52 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -713,7 +713,7 @@ class FetchFSM(ControlBase):
         # set priv / virt mode on I-Cache, sigh
         if isinstance(self.imem, ICache):
             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
-            comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR])
+            comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 
         with m.FSM(name='fetch_fsm'):