From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 9 May 2020 15:18:53 +0000 (-0400)
Subject: Add shift left opcode to main_stage
X-Git-Tag: div_pipeline~1310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=267854d312c4959a60be5593f3aad1cbf5380113;p=soc.git

Add shift left opcode to main_stage
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 7d79b1a1..6ba4b0b2 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -38,10 +38,12 @@ class ALUMainStage(PipeModBase):
                 comb += self.o.o.eq(self.i.a | self.i.b)
             with m.Case(InternalOp.OP_XOR):
                 comb += self.o.o.eq(self.i.a ^ self.i.b)
+            with m.Case(InternalOp.OP_SHL):
+                comb += self.o.o.eq(self.i.a << self.i.b)
 
         ###### sticky overflow and context, both pass-through #####
 
-        comb += so.eq(self.i.so)
+        comb += self.o.so.eq(self.i.so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m
diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index 188ea4ab..f71c59cc 100644
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -1,7 +1,7 @@
 # This stage is intended to handle the gating of carry and overflow
 # out, summary overflow generation, and updating the condition
 # register
-from nmigen import (Module, Signal, Cat)
+from nmigen import (Module, Signal, Cat, Repl)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
@@ -23,10 +23,16 @@ class ALUOutputStage(PipeModBase):
         comb = m.d.comb
 
         o = Signal.like(self.i.o)
+        o2 = Signal.like(self.i.o)
         with m.If(self.i.ctx.op.invert_out):
-            comb += o.eq(~self.i.o)
+            comb += o2.eq(~self.i.o)
         with m.Else():
-            comb += o.eq(self.i.o)
+            comb += o2.eq(self.i.o)
+
+        with m.If(self.i.ctx.op.is_32bit):
+            comb += o.eq(Cat(o2[0:32], Repl(0, 32)))
+        with m.Else():
+            comb += o.eq(o2)
 
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index a9ac703d..9b9152b1 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -76,7 +76,7 @@ class ALUTestCase(FHDLTestCase):
                     vld = yield alu.n.valid_o
                 yield
                 alu_out = yield alu.n.data_o.o
-                self.assertEqual(simulator.gpr(3), SelectableInt(alu_out, 64))
+                self.assertEqual(simulator.gpr(3).value, alu_out)
 
         sim.add_sync_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -124,6 +124,16 @@ class ALUTestCase(FHDLTestCase):
             with Program(lst) as program:
                 sim = self.run_tst_program(program, initial_regs)
 
+    def test_rlwinm(self):
+        for i in range(0, 10):
+
+            lst = ["slw 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, 63)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
+
     def test_ilang(self):
         rec = CompALUOpSubset()