From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 18:58:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2682b60795fdc58a1665159e90bbf9fc3f307580;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 3766c12a8..97bf4d4c3 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -6,7 +6,6 @@ Links:
 
 * [[discussion]]
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions>
-* <http://0x80.pl/notesen/2016-10-23-avx512-conflict-detection.html> conflictd example
 * <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-May/004884.html>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=142> specialist vector ops
@@ -14,12 +13,12 @@ Links:
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
 
-The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism.
+The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism.
 Therefore there are not that many cases where *actual* Vector
 instructions are needed. If they are, they are more "assistance"
 functions.  Two traditional Vector instructions were initially
 considered (conflictd and vmiota) however they may be synthesised
-from existing SVP64 instructions and have been moved to [[discussion]]
+from existing SVP64 instructions: details in [[discussion]]
 
 Notes: