From: lkcl <lkcl@web>
Date: Wed, 16 Dec 2020 01:23:11 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1306^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26abcb46742932efda2bf5095817c7f2ccbd1a11;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index dda30fd4f..dd44f4c9c 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -46,7 +46,7 @@ Twin Predication (1 src, 1 dest):
 
 ## Predicate MASK Encoding
 
-One bit indicates the mode: CR or Int predication.   The two types may not be mixed.
+One bit (`MASKMODE`) indicates the mode: CR or Int predication.   The two types may not be mixed.
 
 Integer Twin predication has a second set if 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).