From: lkcl <lkcl@web>
Date: Sat, 1 Oct 2022 17:57:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~253
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26b2fbd6319fe0bdeb77a2b91bbe8d84b88e654e;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 16f8afc5c..59d666801 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -10,7 +10,6 @@ Note Power ISA v3.1 p12:
 There are eight SPRs, available in any privilege level:
 
 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
-* SVSRR0 which is used for exceptions and traps to store SVSTATE.
 * SVLR, a mirror of LR, used by Vectorised Branch
 * SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
 * SVREMAP for applying specific shapes to specific registers
@@ -54,7 +53,8 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
 * Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted.
 * UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted.
 * hphint - Horizontal Parallelism Hint. Indicates that
-  no Hazards exist between these elements. In Vertical First Mode
+  no Hazards exist between this number of sequentially-accessed
+   elements (including after REMAP). In Vertical First Mode
    hardware **MUST** perform this many elements in parallel
    per instruction. Set to zero to indicate "no hint".
 * SVme - REMAP enable bits, indicating which register is to be
@@ -143,20 +143,6 @@ Notes:
 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
   than 64 is reserved and will cause an illegal instruction trap.
 
-# SVSRR0
-
-In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
-
-* SRR0 to store the PC (CIA/NIA)
-* SRR1 to store a copy of the MSR
-
-Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.  Thus, at an exception point,
-hardware **must** save/restore SVSTATE in SVSRR0 at exactly the same
-time that SRR0 is saved/restored in PC and SRR1 in MSR.
-
-The SPR name given for the purposes of saving/restoring
-SVSTATE is SVSRR0.
-
 # SVLR
 
 SV Link Register, exactly analogous to LR (Link Register) may