From: lkcl <lkcl@web>
Date: Mon, 14 Dec 2020 01:52:35 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26b8c1d3c448e44f55c5dbfd5262a1dda9a9247c;p=libreriscv.git

---

diff --git a/openpower/sv/example_dep_matrices.mdwn b/openpower/sv/example_dep_matrices.mdwn
index 554d27e56..142c95384 100644
--- a/openpower/sv/example_dep_matrices.mdwn
+++ b/openpower/sv/example_dep_matrices.mdwn
@@ -22,4 +22,4 @@ See <https://bugs.libre-soc.org/show_bug.cgi?id=213#c83>
 Register allocation associated with this DM layout: Vectors may *only* be allocated to Vector FPs if RA%4 == RB%4
 == RT%4 and all reg numbers are over 32.  otherwise they are allocated
 to *scalar* FUs which has significantly less computational resources
-but far greater crossbar routing.
+but far greater crossbar routing.  This allows 4R1W regfiles to be used where normally ultra-costly 12R10W would be required.