From: rwilbur <rwilbur@web>
Date: Thu, 16 Sep 2021 00:29:03 +0000 (+0100)
Subject: Revise spelling:  RISK5 -> RISC-V
X-Git-Tag: DRAFT_SVP64_0_1~112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26ca6d487ccab840ec233fc0773e3ffe4803d649;p=libreriscv.git

Revise spelling:  RISK5 -> RISC-V
---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index b6c10412b..89fbcfe1a 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -137,7 +137,7 @@ Actual Vector Processor Architectures and ISAs:
 * Cray ISA
   <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
 
-* RISK5 RVV
+* RISC-V RVV
   <https://github.com/riscv/riscv-v-spec>
 
 * MRISC32 ISA Manual (under active development)