From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 00:58:28 +0000 (-0700)
Subject: Fix for A_WIDTH == 2 but B_WIDTH==3
X-Git-Tag: working-ls180~1208^2~321
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26e461f47da12b79e5b6682f692d81e2721ca0c0;p=yosys.git

Fix for A_WIDTH == 2 but B_WIDTH==3
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 60bc08b48..10dbb8b9a 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -179,7 +179,7 @@ module \$shiftx (A, B, Y);
         assign A_i[i] = A[i*2];
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
-    else if (B_WIDTH < 3) begin
+    else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin
       wire _TECHMAP_FAIL_ = 1;
     end
     else if (B_WIDTH == 3) begin