From: whitequark <cz@m-labs.hk>
Date: Mon, 3 Jun 2019 03:32:30 +0000 (+0000)
Subject: build.{res,plat}: use xdr=0 as default, not xdr=1.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26e6764ccbad77be8d0e2eb4a417f95216831e22;p=nmigen.git

build.{res,plat}: use xdr=0 as default, not xdr=1.

The previous behavior was semantically incorrect.
---

diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py
index 04e8378..f2ff789 100644
--- a/nmigen/build/plat.py
+++ b/nmigen/build/plat.py
@@ -169,7 +169,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
 
     def get_input(self, pin, port, extras):
         self._check_feature("single-ended input", pin, extras,
-                            valid_xdrs=(1,), valid_extras=None)
+                            valid_xdrs=(0,), valid_extras=None)
 
         m = Module()
         m.d.comb += pin.i.eq(port)
@@ -177,7 +177,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
 
     def get_output(self, pin, port, extras):
         self._check_feature("single-ended output", pin, extras,
-                            valid_xdrs=(1,), valid_extras=None)
+                            valid_xdrs=(0,), valid_extras=None)
 
         m = Module()
         m.d.comb += port.eq(pin.o)
@@ -185,7 +185,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
 
     def get_tristate(self, pin, port, extras):
         self._check_feature("single-ended tristate", pin, extras,
-                            valid_xdrs=(1,), valid_extras=None)
+                            valid_xdrs=(0,), valid_extras=None)
 
         m = Module()
         m.submodules += Instance("$tribuf",
diff --git a/nmigen/build/res.py b/nmigen/build/res.py
index 09707ef..88e6006 100644
--- a/nmigen/build/res.py
+++ b/nmigen/build/res.py
@@ -83,7 +83,7 @@ class ConstraintManager:
                 if dir is None:
                     dir = subsignal.io[0].dir
                 if xdr is None:
-                    xdr = 1
+                    xdr = 0
                 if dir not in ("i", "o", "io", "-"):
                     raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"-\", "
                                     "not {!r}"
@@ -93,8 +93,8 @@ class ConstraintManager:
                                      "direction can be changed from \"io\" to \"i\", from \"io\""
                                      "to \"o\", or from anything to \"-\""
                                      .format(subsignal.io[0], subsignal.io[0].dir, dir))
-                if not isinstance(xdr, int) or xdr < 1:
-                    raise ValueError("Data rate of {!r} must be a positive integer, not {!r}"
+                if not isinstance(xdr, int) or xdr < 0:
+                    raise ValueError("Data rate of {!r} must be a non-negative integer, not {!r}"
                                      .format(subsignal.io[0], xdr))
             return dir, xdr
 
diff --git a/nmigen/test/test_build_res.py b/nmigen/test/test_build_res.py
index 1a14eb4..1455619 100644
--- a/nmigen/test/test_build_res.py
+++ b/nmigen/test/test_build_res.py
@@ -215,8 +215,8 @@ class ConstraintManagerTestCase(FHDLTestCase):
 
     def test_wrong_request_with_wrong_xdr(self):
         with self.assertRaises(ValueError,
-                msg="Data rate of (pins o A0) must be a positive integer, not 0"):
-            user_led = self.cm.request("user_led", 0, xdr=0)
+                msg="Data rate of (pins o A0) must be a non-negative integer, not -1"):
+            user_led = self.cm.request("user_led", 0, xdr=-1)
 
     def test_wrong_request_with_xdr_dict(self):
         with self.assertRaises(TypeError,
diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py
index c80076d..3f55bc3 100644
--- a/nmigen/vendor/fpga/lattice_ice40.py
+++ b/nmigen/vendor/fpga/lattice_ice40.py
@@ -117,6 +117,8 @@ class LatticeICE40Platform(TemplatedPlatform):
         return m
 
     def get_input(self, pin, port, extras):
+        self._check_feature("single-ended input", pin, extras,
+                            valid_xdrs=(0,), valid_extras=True)
         return self._get_io_buffer(port, extras, lambda bit: [
             # PIN_NO_OUTPUT|PIN_INPUT
             ("p", "PIN_TYPE",       0b0000_01),
@@ -124,6 +126,8 @@ class LatticeICE40Platform(TemplatedPlatform):
         ])
 
     def get_output(self, pin, port, extras):
+        self._check_feature("single-ended output", pin, extras,
+                            valid_xdrs=(0,), valid_extras=True)
         return self._get_io_buffer(port, extras, lambda bit: [
             # PIN_OUTPUT|PIN_INPUT_REGISTERED
             ("p", "PIN_TYPE",       0b0110_00),
@@ -131,6 +135,8 @@ class LatticeICE40Platform(TemplatedPlatform):
         ])
 
     def get_tristate(self, pin, port, extras):
+        self._check_feature("single-ended tristate", pin, extras,
+                            valid_xdrs=(0,), valid_extras=True)
         return self._get_io_buffer(port, extras, lambda bit: [
             # PIN_OUTPUT_TRISTATE|PIN_INPUT_REGISTERED
             ("p", "PIN_TYPE",       0b1010_00),